Data transfer rates between a host device and peripheral drive devices within a personal computer, PC, system are limited by the bus architecture interconnecting the devices. One type of bus commonly used to interconnect or interface the peripheral drive device to a system bus of a PC is an ATA bus, which is a disk drive interface originally designed for the ISA bus of the IBM PC/AT. The ATA bus was first configured using LS-TTL (Low-power Schottky transistor-transistor logic) gates to drive an 18 inch cable. The slow edges of the LS-TTL gates and the short cable length worked adequately in the then existing systems. However, as PC systems have become faster and more complex, the definition of the ATA bus has been expanded to include operating modes performing faster data transfer rates, and hardware designers have often extended the ATA cable length to well over 18 inches. For example, PIO (programmed I/O) modes now include PIO modes 0-4. Modes 0, 1 and 2 correspond to the ATA interface as originally defined, while PIO Mode 3 defines a maximum data transfer rate of 11.1 MBytes/sec and PIO Mode 4 defines a maximum transfer rate of 16.7 MBytes/sec. Similarly, new DMA modes have been defined. Multiword DMA Mode 0 corresponds to the original interface, while DMA Modes 1 and 2 provide faster data transfer rates. Multiword DMA Mode 2 has the same maximum transfer rate as the new PIO Mode 4.
These new operating modes require higher performance from the ATA bus, resulting in an effort to increase data transfer rates by reducing cycle times. The effort to reduce cycle times has been accomplished by increasing edge rates. The increased edge rates together with the increase in ATA cable length have in turn led to the emergence of weaknesses in the original ATA cabling configuration. These weaknesses affect the integrity of the signals transmitted over the cable. Of particular concern are excessive ringing and crosstalk between signals, and timing/propagation delays which can lead to system failure and/or data loss. Increased edge rates and excessive cable length cause these problems. Thus, the data transfer rate of valid usable data is restricted by limitations inherent to the structure of the ATA bus.
The increased edge rates and excessive cable length are problematic to the ATA bus because it is a poorly terminated bus structure design. The standard 18 inch ATA bus cable is generally modeled as a single-ended transmission line with a characteristic impedance typically of about 110 ohms and a propagation velocity typically of about 60% c. According to transmission line theory, ringing occurs when the termination impedance does not match the characteristic impedance of the cable. The amplitude of ringing is increased with a greater mismatch of impedances. Ringing of sufficient amplitude on signal and data lines of the ATA bus can cause false triggering and excessive settling delays which can lead to system failure and/or data loss.
The occurrence of ringing is especially problematic for data transfers over an ATA bus in PC systems because digital information is being transferred over a transmission line. According to another aspect of transmission line theory, information to be transmitted over the transmission line is input as a waveform. Due to the characteristic impedance and length of the transmission line, the waveform output from the transmission line has some distortion. In analog transmissions where the input waveforms are generally sine waves, the output waveform is typically distorted by a phase shift which can be corrected with relative ease. However, in digital transmissions, the input waveforms are generally some type of square wave, since recognition of an edge transistion is what is important due to the fact that information transmitted is in the form of 1's and 0's. Distortion of these square waves is evident as ringing, which results in a waveform in which the edge transistions cannot be clearly recognized. Thus, chances for false triggering, as mentioned above, are likely and symptomatic of digital transmissions.
The problem of increased ringing has become more prevalent recently because the bus architecture of the modem PC has changed to accommodate increased processor and drive speeds. As processor bus speeds have increased from 8 MHz to 33 MHz and disk drives have increased in speed, it has become necessary to update the ATA standard to allow for faster data transfer rates. To reduce propagation delay, some manufacturers have increased the output drive of the host in order to slew the output signal faster with the capacitive load of the cable. This has been accomplished by implementing the ATA interface chips with fast CMOS processes instead of the low speed TTL devices used in the first ATA buses. As a result, the output impedance has decreased, and the edge rates on the ATA bus have decreased to 1 to 2 ns or less, as opposed to a 5 to 6 ns range of the TTL devices. These fast edges without sufficient terminations have aggravated the ringing on the bus to the point that many system/drive combinations fail to work.
Crosstalk occurs when switching on one signal line causes induced signals in an adjacent or nearby line. A signal couples into an adjacent line by two mechanisms: coupling capacitance and mutual inductance. As a switching signal wavefront propagates down a cable, it couples energy into the adjacent line. Once the energy is in the second line, it propagates in both directions: toward the receiver and toward the source. The magnitude of the coupled signal is proportional to the rate of change of the signal in the primary line. Additionally, the amplitude of the coupled signal is proportional to the total amount of coupling capacitance and mutual inductance, and is therefore proportional to cable length. These crosstalk characteristics make it important to control the slew rate and cable length of newer ATA bus drivers because fast edge rates and resulting ringing on the data lines can couple by crosstalk into adjacent control lines, and cable lengths over 18 inches increase the probability of crosstalk.
An additional concern associated with the poor termination and cable length of an ATA bus design is propagation delay which is further aggravated by cable length violations. As discussed above, the ATA bus was originally defined to have a maximum length of 18 inches. However, today, system designers are hard pressed to design a system in which a host device can be connected to a peripheral drive device within 18 inches. Moreover, some systems are being implemented with dual-ATA interface ports for sharing two ATA cables. These ports are not completely independent of each other, and dual-porting results in an ATA cable which is effectively 36 inches long. These increased cable lengths impose propagation delays associated with the host and peripheral drive devices sending control and data signals back and forth to each other. These propagation delays ultimately affect the data transfer rate and overall performance of the bus.
A further concern related to data transfers over the ATA bus is data integrity. It is important that the data transferred over the bus is valid, and thus there is a desire to provide error detection capability which is reliable and which can be easily implemented. Since words made up of data bits are being transferred over the ATA bus, a bit oriented error detection approach is more practical than a symbol oriented error detection approach. However, conventional bit oriented error detection is impractical for data transfers occurring over the ATA bus, because the conventional bit oriented error detection is a bit-serial approach. The conventional bit error detection procedure generates a cyclic redundancy code (CRC) value by logically manipulating a stream of input data bits using a generator polynomial: EQU G(X)=X.sup.16 +X.sup.12 +X.sup.5 +1.
Each bit of the data stream is shifted sequentially into a CRC logic encoder/decoder by a bit clock operating at a bit cell timing rate. Since the data transfers occurring over the ATA bus are transferring 16-bit words of data, each word is transferred at a clock period equal to 16 times the bit clock. Thus, using the existing bit serial approach operated by a bit clock would require clocking at the frequency of the bit clock, or 16 times the word clock. A further problem of the bit-serial approach is that since the data is being transferred in word units, there is no bit clock available at this part of the ATA interface circuit structure. Thus, the existing bit oriented error detection procedure is not a practical method of providing data integrity for data transfers over the ATA bus.
The above discussed limitations of the ATA bus design have restricted the data transfer capability between a host device and a peripheral drive device to the rates as described above. With the emergence of still faster processors and peripheral devices it is desirous to obtain still faster and accurate data transfer rates between the host and peripheral drive devices. The synchronous DMA, or Ultra DMA, transfer protocol described in U.S. Pat. No. 5,758,188, enabled an increased data transfer rate over the above described prior protocols to approximately 33.3 Mbytes/sec. However, the transfer rate of future peripheral devices will eventually exceed the 33.3 Mbytes/sec transfer rate of the bus interface, causing a bottleneck for performance over the bus interface. Thus, there exists a hitherto unsolved need for an improved, method for performing data transfers between a host device and a peripheral drive device over a bus interface having certain operational limitations, at an increased data transfer rate without violating the operational limitations of the bus interface.